Traditionally integrated circuits have been built in a planar fashion, with a single layer of transistors. New developments in manufacturing process technology allow wafers to be vertically stacked and fine-grained vertical conductors formed between circuits on adjacent dies [1, 2, 3, 4, 5, 6, 7]; U.S. Pat. No. 5,627,106; U.S. Pat. No. 5,877,034; U.S. Pat. No. 5,998,808; U.S. Pat. No. 6,185,122; U.S. Pat. No. 6,034,882. Alternatively, layers of transistor circuits may be interconnected with coarser grain conductors such as coaxial lines, (C-4) solder pads, solder mounds, solder bumps, wire bounds, wire interconnects or embedded wiring as in U.S. Patent Application No. 20010033030; U.S. Patent Application No. 20010033509; U.S. Patent Aapplication No. 20010005059; U.S. Pat. No. 5,495,397; U.S. Pat. No. 5,544,017; U.S. Pat. No. 5,778,529.
It can be useful for each die in a three-dimensional stack of dies to serve a unique purpose. Previous designs implemented in vertically stacked integrated circuit processes used individual mask layouts for each die in the stack [1, 5, 3, 4]; U.S. Pat. No. 5,998,808; U.S. Pat. No. 5,138,437. While extending these circuits to three-dimensions has the effect of reducing global interconnect length, they do little to alleviate the design effort and mask costs associated with each die.
Recent innovations in three-dimensional memories stack separate layers of memory cells on top of a layer of peripheral circuits [7]; U.S. Pat. No. 6,185,122; U.S. Pat. No. 6,034,882; U.S. Pat. No. 5,487,031; U.S. Pat. No. 5,375,085. However, in these designs, both the memory cell layers and the peripheral circuits must be present to provide random access data storage thus requiring at least two sets of layout masks. Furthermore, the three-dimensional techniques described do not apply to digital logic or digital logic coupled with memories.
Die stacking has the potential to increase processing power, chip integration, operating speed and data storage density in the same planar area while minimizing global interconnect lengths. Reducing the stacking interval (distance between adjacent dies) in these technologies reduces wire lengths even further, resulting in reduced power consumption and increased logic speed. However, self-heating effects, alignment issues and circuit yield impose limits on the stack height. As designs move to three dimensions, new design techniques are required to maximize performance while minimizing design effort.